Support for 130nm and 90nm technology is available today with 65nm support available in the first quarter of 2006.

Chip designs suffer from increasingly prohibitive NRE costs, longer design cycles, and increased risk of not achieving first-time silicon success. Lightspeed's mask reconfigurable logic array can reduce chip development time by four to six months, with performance and density near that of standard cell.

"Our mask reconfigurable logic array offers customers the flexibility to optimize the number of customization masks on their chips for performance and density tradeoffs," said Dave Holt, Lightspeed's CEO. "Lightspeed continues to demonstrate industry-leading density and performance, in the range of 80 percent that of traditional standard cell, making our solution very attractive to IDMs, fabless semiconductor companies, and system manufacturers with in-house COT designs."

Logic Array Advantages

Modern semiconductor processes and their standard cell libraries are continually tuned together to enhance yield. Lightspeed's logic array leverages this ongoing work, as Lightspeed's logic array is built from the pre-characterized, pre-qualified standard cells for each process. Competitive solutions are all built of custom gates or cells that do not gain this yield improvement advantage, are of much lower density and performance, and require dramatically higher investment to port to a new process.

By basing a design on Lightspeed's logic array, designers benefit from 90-95 percent of signal nets being immune to signal-integrity problems in the finished chip. Having small, regular, repeated structures at the design layers with the finest pitches enables RET (resolution enhancement technology) for all logic, enhancing yield. Lightspeed's logic array uses buffers instead of high-drive strength cells, further enhancing signal-integrity compliance and reducing electro-migration analysis. The logic array also results in a more uniform and more easily verifiable power grid. All of these features result in reduced risk and enhanced yield for the chip.

Customer IP blocks can efficiently be embedded in the logic array to differentiate the customer's product. With the reconfigurable Lightspeed logic array, the customer can store inventory in a wafer bank, eliminating the need of doing an all-mask revision for each version of a chip, thus lowering inventory risk, development time, and cost.

In addition to their mask reconfigurable logic array, Lightspeed offers mask reconfigurable I/O and embedded test, giving designers a complete package for developing high-performance mask reconfigurable cell-based chips. The I/O can support a wide range of signaling standards in single PHY and a wide range of system interfaces. AutoTest® embedded test architecture provides 98+ percent stuck-at fault coverage with no Design-for-Test (DFT) restrictions and with no user test-vector generation.

About Lightspeed Logic

Lightspeed Logic is the leader in mask reconfigurable logic arrays, I/O and test. Lightspeed's mask reconfigurable logic array is uniquely standard-cell based, enabling rapid deployment on any semiconductor process and providing industry leading performance and density. Culminating nine years of mask-reconfigurable research and development, Lightspeed significantly reduces development time and cost for SoC, ASSP and ASIC designs.

For more information visit http://www.lightspeed.com/

Media Contacts:

Lightspeed Logic
Michael Sydow
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Cain Communications
Patrick Corcoran
503-284-1563
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